256 Element Multiplexed Array
Pin Functions

Pin # Name Function

Typical Value
1 Det Bias Provides detector bias current. 12V
2 Thermistor A One side of the thermistor. Cooler Control
3 TEC + Positive connection to the thermoelectric cooler. 3V, 1A*
4 Vss Ground for the multiplexer. Gnd
5 DAC Clk TTL compatible input which clocks offset correction values into the DAC for each pixel. Timing Diagram
6 Hold Cap Sel TTL input which selects the large hold capacitor (LOW) or the default small hold capacitor (HIGH). See Chart
7 Frame Start TTL compatible input which initiates a readout cycle. Frame Start is clocked on the next rising Pixel Clock edge and data transfer begins on the following Pixel Clock cycle. Timing Diagram
8 N Bias Rst Analog input voltage to override the internally generated 1.6V that is applied to the integration capacitor upon reset. Must be capable of sourcing or sinking 100ľA. Gnd
9 DAC Vh Analog input voltage which sets the high end limit of the offset correction DACs. 0.9V – 3V
10 Mux Out Analog data output controlled by Pixel Clk. 0.5V – 5V
11 DAC Vl Analog input voltage which sets the low end limit of the offset correction DACs. 0.7V – 3V
12 Global Skim Analog input controls the global input skim current. Gnd
13 Det Bias Analog input provides the bias for the detectors. 12V
14 NC No connection. --
15 NC No connection. --
16 NC No connection. --
17 Vdd Power supply voltage for the multiplexer. 7V
18 Vss Ground for the multiplexer. Gnd
19 Int Clk TTL compatible input which sets the integration period. Detector current is integrated while Int Clk is HIGH. Timing Diagram
20 Int Cap 6 Integration capacitor size selection. This TTL input adds 6pF when LOW. See Chart
21 Int Cap 3 Integration capacitor size selection. This TTL input adds 3pF when LOW. See Chart
22 DAC Latch TTL compatible input latches the offset correction data to a pixel register on the rising edge. Timing Diagram
23 Pixel Clk TTL compatible input which controls the data output. Data is output on each rising edge. Timing Diagram
24 DAC Data TTL compatible serial line used to send offset correction data to each pixel, 8 bits, LSB first. The data selects a value between DAC Vl and DAC Vh. Timing Diagram
25 Vdd Power supply voltage for the multiplexer. 7V
26 TEC - Negative connection to the thermoelectric cooler. 0V
27 Thermistor B One side of the thermistor. Cooler Control
28 Case Case connection. Gnd

* Depends on the desired detector temperature and thermal environment.

Integration and Hold Capacitor Selection Settings
Int Cap 6 Int Cap 3 Well Size Recommended 
Hold Cap Setting
LOW LOW 1pF HIGH (Small)
LOW HIGH 4pF HIGH (Small)
HIGH LOW 7pF LOW (Large)
HIGH HIGH 10pF LOW (Large)